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AMD and Strained Silicon

 

Take process, apply more polish, rinse, repeat…

by Josh Walrath

 

            Last week several sources had stories out that AMD had transitioned to strained silicon manufacturing for its 90 nm and 130 nm lines of Athlon 64’s.  While AMD has not officially confirmed this, the stories going around are most likely true.  IBM was one of the first to successfully integrate a strained silicon process into their design (PowerPC), and they were one of the pioneers in getting the technology to work.  Since then Intel has utilized strained silicon for their latest Pentium 4 processors.  It is only natural that AMD be several months behind the fabrication giant in this aspect.  But what exactly does strained silicon bring to the table, and why hasn’t it been a panacea for companies like Intel? 

The Underlying Technology

            Silicon is the primary semiconductor material used in today’s chips.  A semiconductor is characterized by the ability to conduct electricity in certain circumstance, while in others it acts as an insulator.  This ability allows silicon to be used in today’s processors, where tight electrical control is needed to even get the product to work.  Throughout the years the natural ability of silicon has rarely been the problem in getting chips to go faster and faster.  However; with the latest generation of process technology, silicon is now proving to be very problematic to work with and to get high speeds out of.  Many improvements have been made over the years to get it to work better, among them the use of copper interconnects, low-k dielectrics, and silicon on insulator (SOI).  While the copper interconnects did help the speed, the low-k and SOI are mainly there to control leakage and cut down on power requirements (which in effect help out the overall speed because not as much heat is produced, and more power can be applied effectively to the basic transistor).

            Throughout the years though, very little has been done to the silicon substrate.  Some experiments have been done on isotopically pure silicon wafers, which are made of 100% Si-28 (the Si-29 and Si-30 isotopes are removed, which leaves the Si-28 to form a “more perfect crystal lattice” that has vastly improved heat and power characteristics).  While the characteristics of such wafers are superior to standard silicon wafers, the ability to mass produce such wafers at a competitive price has seemingly not become feasible as of yet.  This is unfortunate as isotopically pure silicon has been shown to have upwards of 60% better thermal and electrical efficiency than wafers made up of all three isotopes.

            The one silicon strategy that has proven to be cost effective in mass production is strained silicon.  The basic idea behind this is if silicon atoms can be forcibly pushed apart, then electrons flowing between gates will be less impeded.  Less impedance means better flow and better flow means faster moving electrons, less power consumed, and less heat generated.  The problem with this was finding an economical way to stretch out these atoms.

You can see the relative sizes of the lattices between Si and Si-Ge.  By doping the Si with Ge, the lattice is able to spread out as compared to what pure Si does. (Image courtesy of IBM)

            Luckily for engineers nature already had an answer.  Crystalline structures have a propensity to lineup with each other when in contact with a similar element or compound.  In this case a layer of Si-Ge (silicon germanium) is laid down, and then a layer of pure silicon is deposited on top of that.  The silicon germanium matrix is much more spread out than just pure silicon.  When the new layer of silicon is deposited on top of the silicon germanium, the pure silicon lattice tries to line up with the Si-Ge, and in the process it “stretches out” or, as they term it, becomes “strained”.  This strained layer of silicon becomes the pathway for electrons to flow through between the metal gates.

Here we can see that the pure Si lattice attempts to line up with the Si-Ge lattice, which causes the pure Si to become "strained". (Image courtesy of IBM)

            In laboratory situations, it has been shown that electrons flow through strained silicon 70% faster than in non-strained silicon, and strained chip designs can be 35% faster than a standard design.  I am assuming that this is in very basic ASIC design though.  Once an ASIC becomes much more complex, there are other factors that will influence overall speed, and the performance increases that strained silicon brings will be diminished.

 

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