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 Slowing Down the Process Migration

A refocus on engineering

by Josh Walrath


            This article is directly inspired by this article at EE Design written by Sharon Zohar.  After reading Zohar’s article, I had originally thought to only do a front page blurb about it, but I found that I started to write more and more about it.  I then decided to go ahead and take a jab at a full blown article and commentary of my own.  I would recommend reading the above mentioned article first before going into this one.  I believe the area where this impacts the most is in 3D Graphics chip design.

            The premise of my article supports what Sharon Zohar presents in the aforementioned article, in which many companies that previously relied on newer manufacturing capabilities to increase the performance of their chips will find it no longer economically feasible to advance to the next node upon that new node’s introduction.  The effect of this will be that companies such as ATI and NVIDIA will have to spend much more time reworking basic transistor designs as well as layout to get faster and more compact chips.

            To get a good idea where this is all going, we need to look at CPU designs from AMD and Intel.  Now, CPU’s and 3D Graphics chips are most definitely not the same, but there are great similarities between the two designs.  First off, both designs do feature pipelining, which allows the processor to break data flow and processing down into steps, and allow multiple instructions to be sent through these pipeline in any one clock cycle.  Secondly, both designs make use of internal cache structures that improve data flow and performance.  The third general similarity is that transistor counts on all of these products are all exceeding 100 million+.  The latest GPU’s are in fact starting to look more and more like massively parallel traditional CPU’s due to the transition from traditional pixel pipelines to more general floating point “functional units”.

            The question that should spring into any readers mind is, if all of these designs are starting to become more similar in overall structure, why are current GPU’s running at a max of 530 MHz on the 130 nm process, while CPU’s from AMD and Intel are running 2 GHz+?  The answer to that one is transistor design and layout.  As it was once explained to me, transistor design is the “secret sauce” of any company that manufactures high performance chips.  These designs are typically held very close to the chest of any company, and they are very shy of sharing any of these secrets with competitors.  Design lifecycles also play a significant part in this, as companies like AMD and Intel do not release new processors at the rate that ATI and NVIDIA do, so they have the chance to build in a lot of headroom into their processors in terms of transistor design and transistor layout.  These extra years spent in engineering these products pays off in much higher clock speeds.

            Both AMD and Intel have pretty much reached the limit of their respective 130 nm processes in terms of both transistor performance and die size.  AMD does appear to have a little life left to their 130 nm process with the newly introduced speed grades of the Athlon 64, but the die size of the Athlon 64 really necessitates a shift to 90 nm for AMD to gain any more marketshare.  Both companies are now compelled to go to the 90 nm process to get further speed increases and to optimize the die size.  Both Intel and AMD have hit many snags with the transition to the 90 nm node, and in fact it appears that in the beginning of 2004 Intel had significant problems getting its new Prescott core processor to run as fast as the Northwood core on the 130 nm process.  The transition to 90 nm has been far more expensive than the transition to 130 nm two years ago.

            Other foundry companies such as TSMC and UMC typically lag behind the big boys in terms of process technology, but their way of doing things is a lot more cost effective.  By letting AMD, Intel, and IBM pave the way, these other foundries can get the underlying equipment and optics for less once they have been developed and put on the market.  These foundry companies also have another option that they typically use, and that is to make smaller steps to the next node.  TSMC has always done intermediary steps between the big node changes, such as their 220 nm and 150 nm processes, and now the 110 nm process.  This allows TSMC to improve their processes with much of the latest technology without having to totally retool the entire line to go to the next node.  These intermediate steps allow some speed and die size optimizations without having to spend millions trying to get to the next node.  This also is a great advantage to the ASIC designers as the design libraries do not change as significantly as with the bigger node jumps.


Next: Paving the Way


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