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AMD Athlon X2 3800+ and Athlon 3800+


Same Numbers, Different Results


by Josh Walrath


            It has been about a year now since AMD first released their dual core offerings to the public.  At that time the X2 4800+ just couldn’t be beat in the majority of applications out there.  It even gave the FX-57 a pretty good run for its money in single thread applications, while destroying everything else in multi-threaded applications.  At that time the cost of entry for an X2 started at around $500, which was pretty unpalatable for the majority of buyers out there.  Several months after the initial release, AMD decided to put out a more inexpensive X2.  The X2 3800+ was released to great acclaim, as it was a lot more affordable at the initial $380 price point than the rest of the X2’s that were at $480 and above.

            The X2 3800+ is based on the Manchester core, which is a revision E processor with dual cores and 512 KB of L2 cache per core.  AMD has kept the L1 caches the same since the first Athlon came out, and it features 64 KB of data and 64 KB of instruction L1 cache.  All revision E mainstream cores are obviously not alike.  At the top end we have the Toledo products which are dual core with 1 MB of L2 cache a piece, while Manchester is next in line with dual core and 512 KB of L2, and after that is San Diego with a single core and 1 MB L2, with the final mainstream desktop product being Venice with a single core and 512 KB L2.  AMD does have other revision E cores such as Palermo and Troy, but these are for markets other than that being covered here.

            Revision E was a huge update for AMD on 90 nm.  The first AMD 90 nm desktop cores were based on the Winchester cores, and they carried a lot of the same baggage that had previously hindered the Athlon 64.  While the Winchester did improve upon the Newcastle core in efficiency, as well as being the first 90 nm product out, there were still issues with the memory controller and other power aspects.  The memory controller by itself had some pretty big issues.  The first issue was that the memory timing TRCD had to be advanced one notch up from the DIMM’s specification.  This means that if a high end DIMM has 2:2:2:5 timings, to have a stable system the memory had to be set at 2:3:2:5.  Often the BIOS would automatically do this when it read the EPROM’s from the DIMMS, but in some cases many users experienced a lot of instability unless they jumped the voltage on their DIMMS much higher than specified, or set TRCD up one notch manually.  The second major issue was the use of 4 DIMMS and trying to enable a 1T command rate.  This was simply not possible at PC 3200 speeds with these older cores.

            Revision E cores fixed these issues, as well as expanding the clockspeed envelope of these products while addressing power and heat.  The improved memory controller was more efficient, and the basic design was about 5% faster per clock than the older Winchester core.  The improved power and heat envelope meant faster clocked chips that ran cooler.  In single core applications, the revision E chips were simply the best running products out there.

            To go dual core, AMD took the revision E core and made the necessary improvements to create these new products.  This does not mean that AMD slapped two rev. E cores onto the same piece of silicon and called it good.  The Athlon 64 was developed from the ground up to be dual core, and a lot of little “hooks” were designed into the single core units so that they could seamlessly be placed together in one coherent design.  Now, to get these to work as they should, quite a few changes are apparent between a single core Athlon 64 and the dual core.  Each core is connected to the other through a crossbar controller (System Request Interface), which does several very important jobs.  The main job the crossbar does is to arbitrate main memory accesses for the two cores.  Each core does not have direct access to the memory controller, nor do either of them have a 64 bit memory controller that addresses a single channel of memory.  The memory controller is separate from each core, and the crossbar controller directs the memory controller.  The crossbar also facilitates all communication between the cores.  Cache coherency is absolutely necessary for a multi-processor system to even work, and AMD has implemented the MOESI protocol to make sure that no data errors are made between the caches.


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